Contents • • • • • • • • • • • • • • • • History [ ] In order to achieve rapid industrialization and development after independence, Nigeria needed to invest in the training of a professional workforce. The indispensable need to create more universities to reach this goal was facilitated by the establishment of the University of Lagos in 1962. The Eric Ashby Commission on Post School Certificate and Higher Education was established by the Nigerian Government in May 1959.

Schaum's Outline of Computer Architecture by Nicholas Carter, 078, available at Book Depository with free delivery worldwide. This sophomore-level course explains how com- puters are designed and how they work. We study modern computer design principles using a typical processor. We then learn how efficient memory sys- tems are designed to work closely with the pro- cessor. Next, we study input/output (I/O) systems which bring the.

The Ashby Commission’s report, titled Investment in Education, recommended the establishment of a new university in Lagos, the then Federal Capital, to provide education for students in Economics, Commerce, Business Administration, and Higher Management Studies. In 1961, Advisory Commission was assigned the detailed planning of the new university by the Federal Government. However, whereas the Ashby Commission had envisaged a non-residential institution which would be cited in the business district of Central Lagos, the UNESCO Commission opted for a traditional university, 'a complete all encompassing institution' with residential accommodation on a large campus. Following the acceptance of the UNESCO Commission’s report, the University of Lagos was established on 22 October 1962 on the authority of the University of Lagos Act of 1962. Governance and administration [ ] The act provided for a provisional council for the university, a senate to preside over academic affairs, and a separate council for the College of Medicine.

This was rather unusual for, by authority of the act, the University consisted of two separate institutions—the main university and an autonomous medical school. The link between the two institutions was tenuous at best, consisting of reciprocal representation on both councils and membership in the University Senate by professors in the medical school. The chancellor is the ceremonial head of the university who, in the name of the university, confers all degrees.

The Vice-Chancellor is responsible for the day-to-day running of the university and accountable to the council. The council is responsible for the selection of all vice-chancellors, deputy vice-chancellors and deans of faculty. The responsibility for regulating all teaching, research and academic functions of the university falls on the senate, as set out in the University of Lagos Act and in the Statute of the University of Lagos. Additionally, the interests of the university's students are represented by the Students' Representative Council (SRC), which also selects representatives to the senate and council via the Dean of Student Affairs.

Martha Cecilia Kristine Series Ebook Torrents. Academics and research [ ] The university has remained one of the most competitive in the country in terms of admissions. Notwithstanding, with approximately 57,000 students as of 2013, the University of Lagos has one of the largest student populations of any university in the country. The University of Lagos is among the first generation of universities in Nigeria and also one of the twenty-five federal universities which are overseen and accredited by the. The university has also built a legacy of academic excellence [ ] and is now acclaimed publicly as 'the University of First Choice and the Nation's Pride.' The University of Lagos is a Centre for academic. The university's research activity was one of the major criteria used by the National Universities Commission (NUC) in adjudging the university as the best university in Nigeria at the Nigerian University System Annual Merit Award (NUSAMA) in 2008. Organization [ ] The main campus is located at,, while the Medical Campus of the College of Medicine is located a few kilometers from the main campus at Idi-Araba,, all on the Lagos mainland.

The university has many other residential facilities and services for both staff and students. The University of Lagos has fourteen academic units comprising a broad range of professional faculties and schools. Most faculties are located on the main campus except the Faculties of Pharmacy, Clinical Sciences, Basic Medical Sciences and Dental Sciences, which are located within the College of Medicine in Idi Araba. The College of Medicine is also the site of the. The university also has other centers and institutes in addition to the various departments in its faculties.

The academic bodies of the University consist of the full-time undergraduate programs, the Distance Learning Institute (DLI) and the School of Postgraduate studies (full-time and part-time programs) whose dramatic growth has attracted the sobriquet 'the Lagoon Lighthouse'. The University of Lagos offers many Academic Programs.

A, a RISC microprocessor A reduced instruction set computer, or RISC (pronounced 'risk', /ɹɪsk/), is one whose (ISA) has a set of attributes that allows it to have a lower (CPI) than a (CISC). Various suggestions have been made regarding a precise definition of RISC, but the general concept is that of a computer that has a small set of simple and general instructions, rather than a large set of complex and specialized instructions. Another common RISC trait is their, where memory is only accessed through specific instructions, rather than as a part of most instructions.

Although a number of computers from the 1960s and 70s have been identified as being forerunners of RISCs, the modern concept dates to the 1980s. In particular, two projects at and are most associated with the popularization of this concept. Stanford's would go on to be commercialized as the successful, while Berkeley's gave its name to the entire concept, commercialized as the. Another success from this era were 's efforts that eventually led to the. As these projects matured, a wide variety of similar designs flourished in the late 1980s and especially the early 1990s, representing a major force in the market as well as in, and similar products. RISC ISAs include,,,,,,,,,,, (including ),,, and. In the 21st century, the use of processors in and such as the and devices provided a wide user base for RISC-based systems.

RISC processors are also used in such as the, the fastest on the list in 2011, second at the 2012 list, and fourth at the 2013 list, and, the fastest in 2012 and third in the 2013 list. Contents • • • • • • • • • • • • History and development [ ] A number of systems, going back to the 1960s, have been credited as the first RISC architecture, partly based on their use of approach. The term RISC was coined by of the project, although somewhat similar concepts had appeared before. The designed by in 1964 used a with only two (register+register, and register+immediate constant) and 74 opcodes, with the basic clock cycle being 10 times faster than the memory access time. Partly due to the optimized of the CDC 6600 states that it can be considered as a forerunner of modern RISC systems, although a number of other technical barriers needed to be overcome for the development of a modern RISC system. An IBM RISC microprocessor views the first RISC system as the design which began in 1975 by, and completed in 1980. The 801 was eventually produced in a single-chip form as the in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'.

As the name implies, this CPU was designed for 'mini' tasks, and was also used in the in 1986, which turned out to be a commercial failure. But the 801 inspired several research projects, including new ones at IBM that would eventually lead to the.

The most public RISC designs, however, were the results of university research programs run with funding from the. The VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. The project started in 1980 under the direction of and. Berkeley RISC was based on gaining performance through the use of and an aggressive use of a technique known as. In a traditional CPU, one has a small number of registers, and a program can use any register at any time. In a CPU with register windows, there are a huge number of registers, e.g.

128, but programs can only use a small number of them, e.g. Eight, at any one time. A program that limits itself to eight registers per procedure can make very fast: The call simply moves the window 'down' by eight, to the set of eight registers used by that procedure, and the return moves the window back. The Berkeley RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer designs of the era) RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor, 39 instruction RISC-II in 1983, which ran over three times as fast as RISC-I.

The project grew out of a graduate course by at in 1981, resulted in a functioning system in 1983, and could run simple programs by 1984. The MIPS approach emphasized an aggressive clock cycle and the use of the pipeline, making sure it could be run as 'full' as possible. The MIPS system was followed by the MIPS-X and in 1984 Hennessy and his colleagues formed. The commercial venture resulted in a new architecture that was also called and the in 1985. RISC-V prototype chip (2013). In the early 1980s, significant uncertainties surrounded the RISC concept, and it was uncertain if it could have a commercial future, but by the mid-1980s the concepts had matured enough to be seen as commercially viable. In 1986 started using an early implementation of their in some of their computers.

In the meantime, the effort had become so well known that it eventually became the name for the entire concept and in 1987 began shipping systems with the processor, directly based on the Berkeley RISC-II system. The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system. The success of SPARC renewed interest within IBM, which released new RISC systems by 1990 and by 1995 RISC processors were the foundation of a $15 billion server industry. Since 2010 a new (ISA),, has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the ISA is fixed. The ISA is designed to be extensible from a barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer defined extensions and coprocessors.

It has been tested in silicon design with the ROCKET which is also available as an open source processor generator in the CHISEL language. Characteristics and design philosophy [ ]. For more details on this topic, see. Instruction set philosophy [ ] A common misunderstanding of the phrase 'reduced instruction set computer' is the mistaken idea that instructions are simply eliminated, resulting in a smaller set of instructions. In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs.

Some RISC processors such as the have instruction sets as large as the CISC, for example; conversely, the DEC —clearly a CISC CPU because many of its instructions involve multiple memory accesses—has only 8 basic instructions and a few extended instructions. The term 'reduced' in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the 'complex instructions' of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction. In particular, RISC processors typically have separate instructions for I/O and data processing. [ ] The term is sometimes preferred. Instruction format [ ] Most RISC architectures have fixed-length instructions (commonly 32 bits) and a simple encoding, which simplifies fetch, decode, and issue logic considerably.

One drawback of 32-bit instructions is reduced code density, which is more adverse a characteristic in embedded computing than it is in the workstation and server markets RISC architectures were originally designed to serve. To address this problem, several architectures, such as,,,, and the, have an optional short feature-reduced instruction format or instruction compression feature. The also follows this pattern, albeit having evolved in the opposite direction, having added longer media instructions to an original 16-bit encoding. Hardware utilization [ ] For any given level of general performance, a RISC chip will typically have far fewer dedicated to the core logic which originally allowed designers to increase the size of the register set and increase internal parallelism.

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